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Chief performance architect

Sydney
Bebeeinnovator
Architect
Posted: 14 September
Offer description

Job Overview
We are dedicated to revolutionizing lives with technology that enriches our industry, communities and the world. Our mission is to develop innovative products that accelerate next-generation computing experiences - the building blocks for data centers, artificial intelligence, PCs, gaming and embedded.
The Role
You will lead a team responsible for power optimization and modeling of AMD's data center and gaming GPUs. You will drive innovation to excel in these critical spaces and make strategic decisions that impact the roadmap, execution and market success of DGPU programs.
The Ideal Candidate
You have extensive technical expertise, sound judgement and leadership abilities to drive excellence in processor pipelines and IP blocks at the micro-architectural and RTL level. You have a proven track record of innovation, execution and leadership in achieving world-class Perf/Watt designs. Your excellent interpersonal, communication and leadership skills enable you to motivate and inspire your team.
Lead a team focused on power optimization and modeling for data center and gaming GPUs.
Drive advances in power optimization and modeling to maximize performance within power and cost constraints for AMD graphics platforms.
Collaborate with product teams to understand PPA requirements and translate those into requirements for various IP blocks.
Identify power optimization opportunities, estimate ROI and establish plans with the power optimization team and IP implementation teams.
Develop Architecture and architectural optimization RTL design fixes to deliver optimal designs for Perf/Watt and Perf/$.
Specify Power Test Plans at Graphics Subsystem blocks and at Graphics level, review and sign-off on PTPX/Power Artist data readouts.
Use your expertise to project dynamic power improvements per IP and for whole SOC, providing up-leveled readouts to project leadership and executives.
Guide the development of IP Power Models of different kinds, driving correlation to RTL and Silicon at various stages.
Cultivate and mentor a team of world-class Power Optimization and Modeling engineers.

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