AI Model Engineer Generative HDL & Agentic Design Systems Exclusive Search – Cadence Connect Cadence Connect has been exclusively retained to appoint an AI Model Engineer for a venture-backed deep tech company building AI-native infrastructure for chip design. This is core model ownership, not a wrapper around someone else’s API. You will build, tune and productise the AI systems that generate, refactor and debug real Verilog/SystemVerilog RTL used in real engineering workflows. The Role You will be responsible for the intelligence layer powering a generative chip design platform. In collaboration with the EDA engineers who own simulation and toolchains, you own how the model learns from those signals and how it improves engineering outcomes. This is model AND product. If it doesn’t improve compile rates, test pass rates or repair success, it won't fly. What will you be doing? Core Model Capability Generate clean, maintainable RTL from specifications Refactor and incrementally edit existing RTL without destructive rewrites Preserve ports, signal widths and interface consistency Implement supervised fine-tuning and preference-based optimisation Agentic Workflows Move beyond single-shot generation by building: Spec decomposition and structured outputs Review → critic → repair loops Safe edit patterns that minimise unnecessary diffs Predictable behaviours engineers can trust Data & Evaluation Curate high-quality spec-to-RTL and repair datasets Design synthetic tasks with controlled bug injection Implement compile/test-based quality gates Build benchmarks tracking compile success, test pass rates and regressions Production Readiness Improve latency and responsiveness Contribute to caching, quantisation and versioning strategies Monitor model quality and failure modes, not just uptime What we are looking for 2-5 years in ML engineering, applied research or LLM product development Experience fine-tuning models for structured/code generation Experience building evaluation suites and regression tracking Ability to read/write basic Verilog/SystemVerilog Strong Python (PyTorch preferred) Experience integrating LLMs into multi-step or agent-based workflows Strong engineering discipline and clear communication What does success in this position look like? Measurable gains in HDL generation and repair reliability Improved structured outputs and interface consistency Repeatable training plus evaluation cycles without regressions A dependable AI foundation ready to scale Hybrid working. Australia or Singapore based. Travel as required. Cadence Connect is managing this search exclusively and will provide a detailed briefing to shortlisted candidates. This is an exceptional opportunity for a passionate and dedicated AI Model specialist. For a confidential discussion, please apply or contact mike.priest@cadenceconnect.com.au