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Senior design verification engineer - systemverilog/uvm (melbourne)

Melbourne
Apple
Design
Posted: 4 June
Offer description

Apple Inc. is seeking a DV engineer to ensure bug-free first silicon for IP designs in Melbourne, Australia.

The role requires developing test plans, building verification environments, and using advanced methodologies for quality assurance.

Candidates should hold a Bachelor's degree and have robust knowledge of SystemVerilog, UVM, and verification methodologies.

Preferred qualifications include experience in OOP, scripting languages, and verification tools.

Apple promotes diversity and inclusion within its workforce.

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