As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple's customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test‐plan development, verification environment development (including stimulus and checkers), test‐writing, debug, coverage, and sign‐off for RTL freeze and tape‐out.
Description
In this role, you will be responsible for ensuring bug‐free first silicon for part of the SoC/IP and are encouraged to develop detailed test and coverage plans based on the micro‐architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment, building the verification environment (including stimulus, checkers, assertions, trackers, coverage), and learning to develop verification plans for all features under your care. You will implement verification plans, perform design bring‐up, DV environment bring‐up, enable regression, debug test failures, and track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to use LLM and related technologies to achieve efficient execution and improved quality.
Responsibilities
* Study design specification and create test plan
* Develop infrastructure in SystemVerilog/UVM to stress the design
* Develop and fix failures from regressions, close bugs
* Use LLMs to do verification efficiently
Minimum Qualifications
* Minimum requirement of a bachelors degree
Preferred Qualifications
* BS degree in technical subject area and a minimum 3 years relevant industry experience strongly preferred
* Strong knowledge of OOP, SystemVerilog and UVM
* Strong knowledge in developing scalable and portable test‐benches
* Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
* Some working experience using LLMs for efficiency and quality
* Experience with power‐aware (UPF) or similar verification methodology
* Knowledge of one of the scripting languages such as Python, Perl, TCL
* Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
* Knowledge of formal verification methodology is a plus but not required
* Knowledge of emulation for verification technologies is a plus but not required
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant
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