Posted: 14 September
Offer description
Senior IC Design Engineer
We are seeking a skilled engineer to play a key role in building next-generation Wi-Fi chips that will enable the Internet of Things (IoT).
* Design and development of 802.11ah PHY in Scala (Chisel), System Verilog and C
* Functional verification of 802.11ah PHY in RTL simulators, SDF-annotated gate level simulators and AMS simulators using SystemVerilog, Verilog-A, Matlab, C and Python
* Collaboration with Systems team to achieve optimal performance
* Close work with Analog & RF team to define and improve radio interface
* Development of embedded PHY firmware with Firmware team
* Assistance with silicon bring-up and debug in the lab
* Technical expertise and leadership
* BSc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science
* 3+ years experience as a PHY IC Design Engineer
* Solid understanding of digital signal processing (DSP), with emphasis on HW implementation
* Proven experience developing multiple DSP blocks of in complex SoCs
* An understanding of the IEEE 802.11 PHY layer and familiarity with 802.11ah
* A deep understanding of digital design fundamentals including low power and multi-clock-domain design
* Hands-on experience with the Cadence or Synopsys simulation suite
* Hands-on experience with Linux development environment staples such as make, shell scripts and Python
* Excellent verbal and written communication skills
* Proven ability to work constructively within your team and among other groups
* Strong analytical and problem-solving skills
* A determination to deliver even when subject to time pressures
* A hands-on, practical attitude
* Experience performing phy bring up, debug and performance measurement on silicon in the lab
* A good understanding of embedded processors, familiarity with RISC-V is a plus
* A solid understanding of mixed signal ASIC design and simulation
* Experience using the git revision control tool
* Experience with development and debugging of digital designs from RTL design through
