The Role
AMD's Australian Graphics IP team specialize in the design and verification of AMD's Graphics Processing Units (GPUs). As a Verification Engineer, you will be involved in all aspects of front-end ASIC development including specification, modelling, design, and verification; with a focus on functional and formal verification.
The Candidate
The ideal candidate has 10 to 15 years of experience in industry, has a thorough understanding of all aspects of verification; and can independently build a UVM verification environment or a Formal environment for a complex block.
Key Responsibilities
•Collaborate with architects, modelling engineers, and designers on design specifications
•Develop test plans and specify functional coverage
•Develop and maintain SystemVerilog/UVM test benches
•Develop and maintain formal verification environments
•Analyze and improve coverage of the design
•Identify and implement opportunities for improving AMD's ASIC design and verification environment
Preferred Experience
•Proficient in hardware verification using SystemVerilog/UVM or formal verification methodologies
•Understanding of RTL code written in Verilog or VHDL
•Software development using C or C++
•Debug of hardware or software using industry standard debug tools
•Graphics API or graphics pipeline knowledge is an advantage
•Scripting languages - Python, Perl, shell
•Productivity tools – Jira, Jenkins
•Configuration Management – Perforce, GIT
Academic Credentials
Bachelor level degree in Electrical or Computer Engineering or a related field.