ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.
About AWS: Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
This role is based in Tel Aviv with an option for relocation to the USA (not a must).
Key job responsibilities
Integrate multiple subsystems into top level SOC, ensuring correct clock, reset, functional, and DFT signal routing.
As a key member of the ASIC design team, implement and deliver high performance, area‑and power‑efficient RTL to achieve design targets and specifications.
Analyze design, micro‑architecture or architecture to make trade‑offs based on features, power, performance or area requirements.
Develop micro‑architecture, implement SystemVerilog RTL, and deliver synthesis / timing clean design with constraints.
Perform lint and clock domain crossing quality checks on the design.
Work with architects, other designers, verification teams, pre‑and post‑silicon validation teams, synthesis, timing and back‑end teams to accomplish your tasks.
What you bring
Familiarity with scripting in Python.
Proficiency with assertions.
Good debug skills to analyze RTL test failures.
A “Learn and Be Curious” mindset.
About the team Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud‑Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers, including AWS Inferentia, our custom‑designed machine learning inference datacenter server. We’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail‑blaze new technologies and architectures, while ensuring high design quality and making the right trade‑offs.
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge‑sharing and mentorship.
Basic Qualifications
3+ years in RTL design for SOC.
3+ years of VLSI engineering.
3+ years with code quality tools including Spyglass, LINT, or CDC.
Preferred Qualifications
Experience with micro‑architecture, SystemVerilog RTL, assertions, SDC constraints.
Familiarity with data path design, interconnects, AXI protocol.
Good analytical, problem‑solving, and communication skills.
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