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Role
* Experience in Verilog, SystemVerilog, UVM
* Design and develop testplan
* Develop testcase in UVM/SV, C
* Willing to work independently to develop driver/monitor code
Design and Verification
* Knowledge of APB/AXI/AHB protocol
* Familiarity with MIPI protocol (advantage)
* Knowledge in Perl, Python
Job Details
* Location: Bangalore
* Experience: 1 Year
* Education: B.E, M.Tech
* Salary: 3 LPA
* Seniority Level: Entry level
* Employment Type: Full time
* Job Function: Design, Art/Creative, and Information Technology
* Industries: Semiconductor Manufacturing
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